English
Language : 

ICS952607 Datasheet, PDF (17/21 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor
Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
MAX
UNITS NOTES
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VMID
VIL
IIH
IIL1
IIL2
3.3V +/-5%
3.3V +/-5%
3.3V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pull-
up resistors
VIN = 0 V; Inputs with pull-up
resistors
2
1
VSS -
0.3
-5
-5
-200
VDD + 0.3 V
1.8
V
0.8
V
5
uA
uA
uA
Operating Supply Current IDD3.3OP
Full Active, CL = Full load;
350
Powerdown Current
Input Frequency3
Pin Inductance1
Input Capacitance1
Clk Stabilization1,2
Modulation Frequency
IDD3.3PD
all diff pairs driven
all differential pairs tri-stated
35
12
Fi
VDD = 3.3 V
14.31818
Lpin
7
CIN
Logic Inputs
5
COUT
Output pin capacitance
6
CINX4
X1 & X2 pins
5
TSTAB
From VDD Power-Up or de-
assertion of PD# to 1st clock.
1.8
Triangular Modulation
30
33
mA
mA
mA
MHz 3
nH
1
pF
1
pF
1
pF
1
ms 1,2
kHz
1
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
4 Crystal recommendations: CL = 20pF and Shunt cap. Max = 5pF.
0734—07/16/04
17