ICS952607 Datasheet, PDF (1/21 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 Compliant clock for Next Gen P4 Processor
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 9 - PCI, 3 free running, 33MHz
• 3 - REF, 14.318MHz
• 3 - 3V66, 66.66MHz
• 1 - VCH/3V66, selectable 48MHz or 66MHz
• 2 - 48MHz
• 1 - 24/48MHz
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
• QuadRom^TM frequency selection.
• Programmable output frequency.
• Programmable asynchronous 3V66&PCI frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system if system
malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference input.
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
• Supports CPU clks up to 400MHz
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0
FS4 FS3 FS2 FS1 FS0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
CPU
MHz
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
100.99
201.98
134.65
168.31
115.00
230.00
153.33
191.67
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
105.00
210.00
140.00
175.00
110.00
220.00
146.66
183.34
0734—07/16/04
AGP
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
67.33
67.33
67.33
67.32
76.66
76.66
76.66
76.66
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
Pin Configuration
*FS1/REF0 1
*FS0/REF1 2
REF2 3
VDDREF 4
X1 5
X2 6
GND 7
**FS2/PCICLK_F0 8
**FS4/PCICLK_F1 9
48 VDDA
47 GND
46 IREF
45 Reset#
44 GND
43 CPUCLKT1
42 CPUCLKC1
41 VDDCPU
40 CPUCLKT0
PCICLK_F2 10
VDDPCI 11
GND 12
^^PCICLK0 13
PCICLK1 14
PCICLK2 15
PCICLK3 16
VDDPCI 17
GND 18
PCICLK4 19
PCICLK5 ²⁰
**Sel24_48#/24_48MHz 21
**FS3/48MHz_0 22
48MHz_1 23
GND ²⁴
39 CPUCLKC0
38 GND
37 SRCCLKT
36 SRCCLKC
35 VDD
34 VttPWR_GD/PD#
33 SDATA
32 SCLK
31 3V66_0
30 3V66_1
29 _GND
28 VDD3V66
27 3V66_2
26 3V66_3/VCH
25 _VDD48
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
^^ An external 2.2K pull-down resistor is needed on this pin
48-pin SSOP
Note: FS1 and FS0 are equal to Intel CK409-defined FSA and FSB,
respectively.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.