ICS8761 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
1
2, 16, 17,
21, 25, 29,
33, 48, 52,
56, 60, 64
3, 4
5, 9, 40, 44
6
7
8
10, 11
12
13
14, 15
18, 20,
22, 24
19, 23
26, 28,
30, 32
27, 31
34, 35
36
37
38, 39
41
42
43
45
Name
REF_CLK
Type
Description
Input Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
GND
Power
Power supply ground.
XTAL1,
XTAL2
V_DD
XTAL_SEL
PLL_SEL
V_DDA
D_SELC0,
D_SELC1
OEC
OEA
D_SELA0,
D_SELA1
QA0, QA1,
QA2, QA3
V_DDOA
QB0, QB1,
QB2, QB3
V_DDOB
D_SELB1,
D_SELB0
OEB
OED
D_SELD1,
D_SELD0
MR
FBDIV_SEL1
FBDIV_SEL0
FB_IN
Input
Power
Input
Input
Power
Input
Input
Input
Input
Output
Power
Output
Power
Input
Input
Input
Input
Input
Input
Input
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Core supply pins.
Pullup
Pullup
Selects between crystal oscillator or reference clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects REF_CLK
when LOW. LVCMOS / LVTTL interface levels.
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
Analog supply pin. See Applications Note for filtering.
Pulldown
Pullup
Pullup
Pulldown
Selects divide value for Bank C outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines state of Bank C outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank A outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank A outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Bank A clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank A outputs.
Bank B clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank B outputs.
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Selects divider value for Bank B outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines state of Bank B outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank D outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank D outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Active HIGH Master reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with "zero
delay". LVCMOS / LVTTL interface levels.
8761CY
www.icst.com/products/hiperclocks.html
2
REV. C SEPTEMBER 7, 2004