ICS8761 Datasheet, PDF (1/15 Pages) Integrated Circuit Systems – LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
GENERAL DESCRIPTION
ICS
The ICS8761 is a low voltage, low skew PCI /
PCI-X Clock Generator and a member of the
HiPerClockS™ _{HiPerClockS™family of High Performance Clock}
Solutions from ICS. The ICS8761 has a selectable
REF_CLK or crystal input. The REF_CLK input
accepts LVCMOS or LVTTL input levels. The ICS8761 has a
fully integrated PLL along with frequency configurable clock
and feedback outputs for multiplying and regenerating clocks
with “zero delay”. Using a 20MHz or 25MHz crystal or a
33.333MHz or 66.666MHz reference frequency, the ICS8761
will generate output frequencies of 33.333MHz, 66.666MHz,
100MHz and 133.333MHz simultaneously.
The low impedance LVCMOS/LVTTL outputs of the ICS8761
are designed to drive 50Ω series or parallel terminated
transmission lines.
FEATURES
• Fully integrated PLL
• 17 LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
• Maximum output frequency: 166.67MHz
• Maximum crystal input frequency: 38MHz
• Maximum REF_CLK input frequency: 83.33MHz
• Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz simultaneously
• Separate feedback control for generating PCI / PCI-X
frequencies from a 20MHz or 25MHz crystal or 33.333MHz
or 66.666MHz reference frequency
• Cycle-to-cycle jitter: 70ps (maximum)
BLOCK DIAGRAM
OEA
MR
• Period jitter, RMS: 17ps (maximum)
• Output skew: 230ps (maximum)
• Bank skew: 40ps (maximum)
• Static phase offset: 0 ± 150ps (maximum)
• Full 3.3V or 3.3V core, 2.5V multiple output supply modes
• 0°C to 85°C ambient operating temperature
• Lead-Free package available
D_SELA0
D_SELA1
REF_CLK
0
XTAL1
XTAL2
OSC ¹
XTAL_SEL
FB_IN
PLL_SEL
OEB
D_SELB1
D_SELB0
OEC
D_SELC1
D_SELC0
OED
D_SELD1
D_SELD0
÷3
0
÷4
1
÷6
÷12
PLL
QA0
QA1 PIN ASSIGNMENT
00
QA2
01
QA3
10
11
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
REF_CLK ¹
48 GND
00
QB0 _{GND 2}
01
QB1 XTAL1 3
47 FB_OUT
4 6 VDDOFB
10
QB2 XTAL2 ⁴
11
QB3
VDD ⁵
XTAL_SEL 6
45 FB_IN
44 VDD
43 ^FBDIV_SEL0
PLL_SEL 7
QC0
00
VDDA ⁸
01
QC1
VDD 9
10
QC2 _{D_SELC0 10}
11
QC3 _{D_SELC1 11}
ICS8761
42 ^FBDIV_SEL1
41 MR
40 ^VDD
39 ^D_SELD0
38 D_SELD1
OEC 12
37 OED
QD0 ^{OEA 13}
36 OEB
00
01
QD1 ^{D_SELA0 14}
35 D_SELB0
10
11
D_SELA1
QD2
GND
QD3
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D_SELB1
GND
FBDIV_SEL1
FBDIV_SEL0
÷6
00
÷12
01
FB_OUT
÷16
10
÷20
11
64-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
8761CY
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 7, 2004
1