ICS8761 Datasheet, PDF (10/15 Pages) Integrated Circuit Systems – LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8761 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_DD, V_DDA, and V_DDOx
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each V_DDA.
3.3V
V_DD
.01µF 10Ω
V_DDA
.01µF
10 µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8761 crystal interface is shown in Figure 2. While layout
the PC Board, it is recommended to provide C1 and C2 spare
footprints for frequency fine tuning. For an 18pF parallel reso-
nant crystal, the C1 and C2 are expected to be ~10pF and ~5pF
respectively.
X1
18pF Parallel Cry stal
XTAL2
C1
SPARE
XTAL1
C2
SPARE
FIGURE 2. CRYSTAL INPUT INTERFACE
8761CY
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10
REV. C SEPTEMBER 7, 2004