ICS8761 Datasheet, PDF (11/15 Pages) Integrated Circuit Systems – LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8761
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8761. In this
example, the input is driven by an ICS HiPerClockS LVHSTL
driver. The decoupling capacitors should be physically located
near the power pin. For ICS8761, the unused clock outputs can
be left floating. The optional C1 and C2 are spare footprints for
frequency fine tuning.
VDD
R5 R6
U1
C1
SP
1K 1K
VDD
X1
25MHz,18pF
R7
10
C2
SP
C17
0.1u
C16
10u
VDD
1
2 ^REF_CLK
3 ^GND
4 ^XTAL1
5 ^XTAL2
6 ^VDD
7 ^XTAL_SEL
8
9
PLL_SEL
VDDA
10 ^VDD
11
12
13
14
D_SELC0
D_SELC1
OEC
OEA
15 ^D_SELA0
16
D_SELA1
GND
SP = Spare, Not Install
ICS8761
VDDO
48
GND
FB_OUT
47
46
VDDOFB ₄₅
FB_IN ₄₄
VDD
FBDIV_SEL0
FBDIV_SEL1
MR
43
42
41
40
VDD ₃₉
D_SELD0
D_SELD1
OED
OEB
38
37
36
35
D_SELB0 ₃₄
D_SELB1
GND
33
R1
36
Zo = 50
Zo = 50
R2
36
VDDO
VDD
Zo = 50
R3
36
Receiv er
Receiv er
Receiv er
Logic Input Pin Examples
Set Logic
Set Logic
VDD _{Input to '1'} VDD _{Input to '0'}
RU1
1K
To Logic
Input pins
RD1
SP
RU2
SP
To Logic
Input pins
RD2
1K
VDDO
(U1,5) (U1,9)
VDD
(U1,40)
(U1,44)
C6
C5
C4
C3
0.1u
0.1u
0.1u
0.1u
R4
36
VDD=3.3V
VDDO=3.3V
Zo = 50
Receiv er
(U1,19) (U1,23) (U1,27) (U1,31) (U1,50) (U1,54) (U1,58) (U1,62) (U1,46)
VDDO
C7
C8
C9
C10
C11
C12
C13
C14
C15
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
FIGURE 3. ICS8761 CLOCK GENERATOR SCHEMATIC EXAMPLE
8761CY
www.icst.com/products/hiperclocks.html
11
REV. C SEPTEMBER 7, 2004