IC42S16100 Datasheet, PDF (8/78 Pages) Integrated Circuit Solution Inc – 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

IC42S16100
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
Symbol Parameter
—
—
tCAC
tRCD
tRAC
tRC
tRAS
tRP
tRRD
tCCD
tDPL
tDAL
tRBD
tWBD
tRQL
tWDL
tPQL
tQMD
tDMD
tMCD
Clock Cycle Time
Operating Frequency
CAS Latency
Active Command To Read/Write Command Delay Time
RAS Latency (tRCD + tCAC)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Command Period (ACT[0] to ACT [1])
Column Command Delay Time
(READ, READA, WRIT, WRITA)
Input Data To Precharge Command Delay Time
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
Burst Stop Command To Output in HIGH-Z Delay Time
(Read)
Burst Stop Command To Input in Invalid Delay Time
(Write)
Precharge Command To Output in HIGH-Z Delay Time
(Read)
Precharge Command To Input in Invalid Delay Time
(Write)
Last Output To Auto-Precharge Start Time (Read)
DQM To Output Delay Time (Read)
DQM To Input Delay Time (Write)
Mode Register Set To Command Delay Time
-5
-6
-7
Units
5
6
7
ns
200
166
143 MHz
3
3
3
cycle
3
3
3
cycle
6
6
6
cycle
10
10
10
cycle
6
6
6
cycle
3
3
3
cycle
2
2
2
cycle
1
1
1
cycle
2
2
2
cycle
5
5
5
cycle
3
3
3
cycle
0
0
0
cycle
3
3
3
cycle
0
0
0
cycle
–2
–2
–2
cycle
2
2
2
cycle
0
0
0
cycle
2
2
2
cycle
AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)
Input
CLK
2.4V
1.4V
0.4V
2.4V
INPUT 1.4V
0.4V
tCK
tCHI
tCL
tCS
tCH
tAC
tOH
OUTPUT
1.4V
1.4V
Output Load
ZO = 50Ω
I/O
50 Ω
30 pF
+1.4V
8
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004