IC42S16100 Datasheet, PDF (7/78 Pages) Integrated Circuit Solution Inc – 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

IC42S16100
AC CHARACTERISTICS^(1,2,3)
Symbol
tCK3
tCK2
tAC3
tAC2
tCHI
tCL
tOH
tLZ
tHZ3
tHZ2
tDS
tDH
tAS
tAH
tCKS
tCKH
tCKA
tCS
tCH
tRC
tRAS
tRP
tRCD
tRRD
tDPL
tDAL
tT
tREF
Parameter
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
Access Time From CLK⁽⁴⁾
CAS Latency = 3
CAS Latency = 2
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
Output LOW Impedance Time
Output HIGH Impedance Time⁽⁵⁾
CAS Latency = 3
CAS Latency = 2
Input Data Setup Time
Input Data Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
CKE to CLK Recovery Delay Time
Command Setup Time (CS, RAS, CAS, WE, DQM)
Command Hold Time (CS, RAS, CAS, WE, DQM)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
Input Data To Precharge
Command Delay time
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
Transition Time
Refresh Cycle Time (4096)
-5
Min. Max.
5—
7—
— 4.5
—5
2—
2—
2—
0—
— 4.5
—5
2—
1—
2—
1—
2—
1—
1CLK+3 —
2—
1—
50 —
30 100,000
15 —
15 —
10 —
2CLK —
-6
Min. Max.
6—
8—
— 5.5
—6
2—
2—
2—
0—
— 5.5
—6
2—
1—
2—
1—
2—
1—
1CLK+3 —
2—
1—
60 —
36 100,000
18 —
18 —
12 —
2CLK —
-7
Min. Max Units
7 — ns
8.6 — ns
— 6 ns
— 6 ns
2.5 — ns
2.5 — ns
2 — ns
0 — ns
— 6 ns
— 6 ns
2 — ns
1 — ns
2 — ns
1 — ns
2 — ns
1 — ns
1CLK+3 — ns
2 — ns
1 — ns
70 — ns
42 100,000 ns
21 — ns
21 — ns
14 — ns
2CLK — ns
2CLK+tRP — 2CLK+tRP — 2CLK+tRP — ns
1 10
— 64
1 10
— 64
1 10 ns
— 64 ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated
voltages. Also note that the power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and
VIL (max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL
(max.) when the output is in the high impedance state.
Integrated Circuit Solution Inc.
7
DR024-0D 06/25/2004