IC42S16100 Datasheet, PDF (62/78 Pages) Integrated Circuit Solution Inc – 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

IC42S16100
Read Cycle / Ping Pong Operation (Bank Switching)
T0
T1
T2
T3
CLK
tCKS
CKE
tCS
CS
RAS
tCHI
tCK
tCL
tCKA
tCH
tCS
tCH
CAS
WE
A0-A9
tCS
tCH
tCS
tCH
tAS
tAH
ROW
tAS
tAH
A10
ROW
tAS
tAH
A11
BANK 0
DQM
I/O
tRRD
(BANK 0 TO 1)
tRCD
(BANK 0)
tRAS
(BANK 0)
tRC
(BANK 0)
<ACT 0>
CAS latency = 3, burst length = 2
T4
T5
T6
T7
T8
T9 T10
T11 T12
(1)
ROW COLUMN
AUTO PRE
ROW
NO PRE
BANK 1 BANK 0
tCS
(1)
COLUMN
AUTO PRE
NO PRE
BANK 1
tQMD
BANK 0 OR 1
BANK 0
ROW
ROW
BANK 0 OR 1
BANK1
BANK 0
tCH
tRCD
(BANK 1)
tCAC
(BANK 0)
<ACT1> <READ 0>
<READA 0>
tAC
tAC
tLZ
tOH
DOUT 0m
tAC
tOH
DOUT 0m+1
tAC
tOH
DOUT 1m
tOH
DOUT 1m+1
tCAC
(BANK 1)
tRQL
(BANK 0)
tRP
(BANK 0)
tRAS
(BANK 1)
tRC
(BANK 1)
<READ 1>
<READA 1>
<PRE 0>
tRP
(BANK1)
tHZ
tRCD
(BANK 0)
tRAS
(BANK 0)
tRC
(BANK 0)
<PRE 1> <ACT 0>
Undefined
Don’t Care
Note 1: A8,A9 = Don't Care.
62
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004