IC42S16100 Datasheet, PDF (31/78 Pages) Integrated Circuit Solution Inc – 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

IC42S16100
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (tWDL) from the precharge command to the point
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write data
recovery period (tDPL) has elapsed. Therefore, the
precharge command must be executed on one clock cycle
that follows the input of the last burst data item.
CAS Latency
3
2
tWDL
0
0
tDPL
1
1
CLK
COMMAND
WRITE A0
tWDL=0
PRE 0
DQM
I/O
DIN A0 DIN A1 DIN A2 DIN A3
WRITE (CA=A, BANK 0)
CAS latency = 2, 3, burst length = 4
MASKED BY DQM
PRECHARGE (BANK 0)
CLK
COMMAND WRITE A0
tDPL
PRE 0
I/O
DIN A0 DIN A1
WRITE (CA=A, BANK 0)
CAS latency = 2, 3, burst length = 4
DIN A2
DIN A3
PRECHARGE (BANK 0)
Integrated Circuit Solution Inc.
31
DR024-0D 06/25/2004