IC41LV44002A Datasheet, PDF (8/20 Pages) Integrated Circuit Solution Inc – 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
AC CHARACTERISTICS (Continued)^{(1,2,3,4,5,6)}
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tCOH
tOFF
tWHZ
tCSR
tCHR
tRPC
tORD
tREF
tT
Parameter
OE Hold Time from WE during
READ-MODIFY-WRITE cycle⁽¹⁸⁾
Data-In Setup Time^{(15, 22)}
Data-In Hold Time^{(15, 22)}
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle⁽¹⁴⁾
CAS to WE Delay Time^{(14, 20)}
Column-Address to WE Delay Time⁽¹⁴⁾
EDO Page Mode READ or WRITE
Cycle Time
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge⁽¹⁵⁾
EDO Page Mode READ-WRITE
Cycle Time
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS^{(13,15,19, 24)}
Output Disable Delay from WE
CAS Setup Time (CBR REFRESH)^{(20, 25)}
CAS Hold Time (CBR REFRESH)^{( 21, 25)}
RAS to CAS Precharge Time
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Auto Refresh Period
2,048 Cycles
Transition Time (Rise or Fall)^{(2, 3)}
1
-50
Min. Max.
8
−
0
−
8
−
108 −
64
−
26
−
39
−
20
−
50 100K
−
30
56
−
5
−
0
12
3
10
5
−
8
−
5
−
0
−
−
32
50
1
AC TEST CONDITIONS
Output load:
Two TTL Loads and 100 pF (Vcc=5.0V±10%)
One TTL Loads and 100 pF (Vcc=3.3V±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V
Output timing reference levels: VOH = 2.0V, VOL = 0.8V
-60
Min. Max.
10
−
0
−
10
−
133 −
77
−
32
−
47
−
25
−
60 100K
−
35
68
−
5
−
0
15
3
10
5
−
10
−
5
−
0
−
−
32
50 ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
8
Integrated Circuit Solution Inc.
DR026-0A 09/04/2001