IC41LV44002A Datasheet, PDF (6/20 Pages) Integrated Circuit Solution Inc – 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
ELECTRICAL CHARACTERISTICS⁽¹⁾
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
−5
5
µA
IIO
Output Leakage Current
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
−5
5
µA
VOH
Output High Voltage Level
IOH = −5.0 mA with VCC=5V
IOH = −2.0 mA with VCC=3.3V
2.4
−
V
VOL
Output Low Voltage Level
ICC1
Standby Current: TTL
IOL = 4.2 mA with VCC=5V
IOL = 2 mA with VCC=3.3V
RAS, CAS ≥ VIH
ICC2
Standby Current: CMOS
RAS, CAS ≥ VCC − 0.2V
ICC3
Operating Current:
RAS, CAS,
Random Read/Write^(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
−
5V
−
3.3V −
5V
−
3.3V −
-50
−
-60
−
0.4
V
2 mA
2
1 mA
0.5
120 mA
110
ICC4
Operating Current:
RAS = VIL, CAS,
EDO Page Mode^(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
-50
−
90 mA
-60
−
80
ICC5
Refresh Current:
RAS, CAS Cycling
CBR^(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-50
−
120 mA
-60
−
110
ICCS
Self Refresh current⁽⁶⁾
Self Refresh Mode
5V,nromal version
5V, L version
500 µA
350
3.3V, normal version 450
3.3, L version
350
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6. ICCS is for S version only.
6
Integrated Circuit Solution Inc.
DR026-0A 09/04/2001