IC41LV44002A Datasheet, PDF (2/20 Pages) Integrated Circuit Solution Inc – 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• Extended Data-Out (EDO) Page Mode
access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% or 3.3V ± 10%
• Self Refresh 2048 cycles for S version
• Low power for L version.
PRODUCT SERIES OVERVIEW
Part No.
Refresh
Voltage
IS41C44002A
2K
5V ± 10%
IS41C44002AS(L)
2K
5V ± 10%
IS41LV44002A
2K
3.3V ± 10%
IS41LV44002AS(L) 2K
3.3V ± 10%
PIN CONFIGURATION
24 Pin SOJ, TSOP-2
VCC 1
I/O0 2
I/O1 3
WE 4
RAS 5
NC 6
24 GND
23 I/O3
22 I/O2
21 CAS
20 OE
19 A9
A10 7
A0 8
A1 9
A2 10
A3 11
VCC 12
18 A8
17 A7
16 A6
15 A5
14 A4
13 GND
DESCRIPTION
The ICSI 44002 Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. These devices
offer an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 2,048 random accesses within a single
row with access cycle time as short as 20 ns per 4-bit word.
These features make the 44002 Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 44002 Series is packaged in a 24-pin 300mil SOJ and a 24
pin TSOP-2
KEY TIMING PARAMETERS
Parameter
RAS Access Time (tRAC)
CAS Access Time (tCAC)
Column Address Access Time (tAA)
EDO Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
-50 -60 Unit
50 60 ns
13 15 ns
25 30 ns
20 25 ns
84 104 ns
PIN DESCRIPTIONS
A0-A10
I/O0-3
WE
OE
RAS
CAS
Vcc
GND
NC
Address Inputs (2K Refresh)
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR026-0A 09/04/2001