IC41LV44002A Datasheet, PDF(18/20 Page) Integrated Circuit Solution Inc – 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

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IC41LV44002A Datasheet, PDF (18/20 Pages) Integrated Circuit Solution Inc – 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

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IC41C44002A/IC41C44002AS(L)

IC41LV44002A/IC41LV44002AS(L)

CBR REFRESH CYCLE (Addresses; OE = DON'T CARE, WE=HIGH)

RAS

tRPC

tCP

CAS

I/O

tRP

tRAS

tCHR

tCSR

tRPC

tRP

tRAS

tCSR

tCHR

Open

HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)

RAS

tCRP

CAS

tRAS

tRCD

tRP

tRSH

tASR

ADDRESS

Row

I/O

tRAD

tRAH tASC

Open

tRAL

tCAH

Column

tAA

tRAC

tCLZ

tCAC

tOE

tORD

tRAS

tCHR

tOFF(2)

Valid Data

Open

tOD

Notes:

1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.

2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.

Integrated Circuit Solution Inc.

DR026-0A 09/04/2001

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