IC61SF12832 Datasheet, PDF (13/17 Pages) Integrated Circuit Solution Inc – 128K x 32 Flow Through SyncBurst SRAM

IC61SF12832
IC61SF12836
WRITE CYCLE TIMING
CLK
ADSP
ADSC
ADV
A16-A0
GW
BWE
BW4-BW1
CE
CE2
CE2
tKC
tKH
tKL
tSS
tSH
ADV must be inactive for ADSP Write ^tAVS
tAS
tAH
WR1
tWS
WR2
tWH
ADSP is blocked by CE inactive
ADSC initiate Write
tAVH
WR3
tWS
tWH
tWS
tWH
tWS
tWH
WR1
WR2
WR3
tCES
tCEH
CE Masks ADSP
tCES
tCEH
tCES
tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
OE
DATAOUT
High-Z
tDS
tDH _{BW4-BW1 only are applied to first cycle of WR2}
DATAIN
High-Z
1a
2a
2b
2c
2d
3a
Single Write
Burst Write
Write
Unselected
Integrated Circuit Solution Inc.
13
SSR018-0A 09/17/2001