IC61SF12832 Datasheet, PDF (11/17 Pages) Integrated Circuit Solution Inc – 128K x 32 Flow Through SyncBurst SRAM

IC61SF12832
IC61SF12836
READ/WRITE CYCLE TIMING
CLK
ADSP
ADSC
tKC
tKH
tKL
tSS
tSH
tSS
tSH
ADSP is blocked by CE inactive
ADV
A16-A0
GW
BWE
BW4-BW1
CE
CE2
CE2
OE
DATAOUT
DATAIN
tAS
tAH
RD1
WR1
RD2
tWS
tWH
tWS
tWH
tCES
tCEH
tWS
tWH
WR1
CE Masks ADSP
tCES
tCEH
CE2 and CE2 only sampled with ADSP or ADSC
tCES
tCEH
tOEQ
tOEHZ
tOELZ
High-Z
1a
tKQLZ
tKQ
High-Z
Single Read
tOEQX
tKQX
tKQHZ
1a
tDS
tDH
Single Write
2a
2b
2c
Burst Read
RD3
Unselected with CE2
tKQX
2d
tKQHZ
Unselected
Integrated Circuit Solution Inc.
11
SSR018-0A 09/17/2001