IC-TW8_16 Datasheet, PDF (9/67 Pages) IC-Haus GmbH – 16-BIT SIN/COS INTERPOLATOR

iC-TW8 16-BIT SIN/COS INTERPOLATOR
WITH AUTO-CALIBRATION
Rev C2, Page 9/67
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = 3.1...5.5 V, Tj = -40...+125 °C, reference point AVSS unless otherwise stated
Item Symbol Parameter
No.
Conditions
Min. Typ.
Total Device
001 AVDD, Permissible Supply Voltage
3.1
DVDD AVDD, DVDD
002 IDD
Total Supply Current in AVDD fin = 1 kHz, Increments 4096, Post-AB Divider 1,
and DVDD
error-free boot-up from EEPROM;
VDD = 5 V, 32 MHz crystal
25
VDD = 3.3 V, 20 MHz crystal
12
Signal Inputs and Amplifiers: SIN+, SIN-, COS+, COS-
101 Vin()
Permissible Input Voltage Range refer to Figure 1
1.4
102 V_IN()
103 V_IN()diff
104 Vos()
105 Iin()
107 OFFcorr
Permissible Input Amplitude
Permissible Input Amplitude,
differential
Amplifier Input Offset Voltage
Input Leakage Current
Correctable Input Offset Voltage
refer to Figure 1
as percentage of input signal amplitude; input
offset voltage is the sum of sensor offset plus
amplifier offset (item 104);
±100
Unit
Max.
5.5
V
35
mA
20
mA
AVDD - V
1.0
700 mVpp
1.4 Vpp
±15 mV
±50 nA
%
108 Acorr
Correctable SIN/COS Amplitude max(Asin, Acos) / min(Asin, Acos), whereas 1.24
Mismatch
Asin and Acos are the SIN/COS input ampli-
tudes respectively.
109 PHIcorr
Correctable SIN/COS Phase
Error
(step size 0.052 degree)
±53
deg
110 Rpu()
Pull-Up Resistor at SIN+, COS+ MAIN_CFG.pull = 1
3
MΩ
111 Rpd()
Pull-Down Resistor at SIN-, COS- MAIN_CFG.pull = 1
Index Signal Inputs and Amplifier: ZERO+, ZERO-
201 Vin()
Permissible Input Voltage
0
202 Vos()
Input Referred Offset Voltage
203 Iin()
Input Leakage Current
Converter Performance
301 INL
Integral Nonlinearity
refer to Figure 3, 1 Vpp-diff SIN/COS input with
compensated offset, gain and phase
302 DNL
Differential Nonlinearity
refer to Figure 3, 1 Vpp-diff SIN/COS input with
compensated offset, gain and phase
303 N
Output Angle Noise
1 Vpp-diff SIN/COS input, fin = 0 Hz
305 tp()io
Input-to-Output Latency
fosc = 32 MHz;
MAIN_FLTR.fb = 0 (lag recovery disabled)
MAIN_FLTR.fb = 1 (lag recovery enabled)
fosc = 24 MHz;
MAIN_FLTR.fb = 0 (lag recovery disabled)
MAIN_FLTR.fb = 1 (lag recovery enabled)
Clock: XIN, XOUT
401 fxtl
Permissible External Frequency AVDD, DVDD = 5 V
6
driven into XOUT
AVDD, DVDD = 3.3 V
6
402 fosc
Internal Oscillator Frequency
AVDD, DVDD = 5 V, permissible maximum
Tj = 27 °C, MAIN_CLOCK.freq = 0
403 TCosc
404 VCosc
AVDD, DVDD = 3.3 V, permissible maximum
Tj = 27 °C, MAIN_CLOCK.freq = 0
Internal Oscillator Temperature AVDD, DVDD = 5 V
Dependancy
AVDD, DVDD = 3.3 V
Internal Oscillator Power Supply
Dependancy
3
MΩ
AVDD V
±15 mV
±50 nA
0.08 deg
0.02 deg
0.08 deg
24
µs
4
µs
32
µs
5.3
µs
32 MHz
24 MHz
32 MHz
20
MHz
24 MHz
18
MHz
-0.07
%/K
-0.09
%/K
1.18
MHz/V