IC-TW8_16 Datasheet, PDF (10/67 Pages) IC-Haus GmbH – 16-BIT SIN/COS INTERPOLATOR

iC-TW8 16-BIT SIN/COS INTERPOLATOR
WITH AUTO-CALIBRATION
Rev C2, Page 10/67
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = 3.1...5.5 V, Tj = -40...+125 °C, reference point AVSS unless otherwise stated
Item Symbol Parameter
No.
Conditions
Unit
Min. Typ. Max.
Reset and Start-Up: xRST
601 DVDDon DVDD Reset Threshold
increasing voltage at DVDD;
xRST tied to DVDD
xRST connected through 68 kΩ to DVSS
2.7
V
4.0
V
602 Vt()hi
Input Logic Threshold High
increasing voltage at xRST
2.7
V
603 Vt()lo
Input Logic Threshold Low
0.8
V
604 Rpu()
Pull-Up Resistor
V() = 0 ... DVDD - 1 V
40
kΩ
605 tstart
Startup Time
AVDD, DVDD = 5 V, fxtl = 24 MHz by crystal;
pin configuration (EEPROM connected)
ready for serial configuration:
EEPROM connected
no EEPROM, SDA = AVSS
no EEPROM, SDA = AVDD
100
ms
100
ms
10
ms
100
ms
606 td()lo
Low-Level Duration for Reset
Triggering
V(xRST) < Vt(xRST)lo
10
ns
Digital Input Pins:
EESEL, CALIB, CLOCK, IR, FRAME, SPI_SI, SPI_SCLK, SPI_xSS, PINSEL, SCL, SDA, FAB
701 Vt()hi
Input Logic Threshold High
DVDD = 5 V
DVDD = 3.3 V
2.2
V
2.2
V
702 Vt()lo
Input Logic Threshold Low
DVDD = 5 V
DVDD = 3.3 V
0.8
V
0.8
V
703 Vt()hi
Input Logic Threshold High
CALIB, SPI_SCLK
DVDD = 5 V
DVDD = 3.3 V
3.75
V
2.47
V
704 Vt()lo
Input Logic Threshold Low
CALIB, SPI_SCLK
DVDD = 5 V
DVDD = 3.3 V
0.75
V
0.49
V
706 Ilk()
Input Leakage Current at
SPI_SI, SPI_SCLK, SPI_xSS
±50 nA
707 Rpu()
Pull-Up Resistor at IR
150
kΩ
708 Rpu()
Pull-Up Resistor at
CALIB, SCL, SDA
10
kΩ
709 Rpd()
Pull-Down Resistor at EESEL,
CLOCK, FRAME, PINSEL
150
kΩ
710 Rpd()
Pull-Down Resistor at FAB
4
kΩ
711 tstore
Required CALIB Wait Time for writing of 150 bytes after CALIB lo → hi;
Parameter Storage to EEPROM for EEPROM with write time of 5 ms
for EEPROM with write time of 2 ms
770 ms
320 ms
Digital Output Pins:
CLOCK, IR, FRAME, SPI_SO, OUTA, OUTB, OUTZ, STATUS, FAULT, SCL, SDA, WP
801 Vs()hi
Output Voltage High
pins SCL, SDA excluded;
DVDD = 5 V, IOUT = 4 mA
4.4
V
DVDD = 3.3 V, IOUT = 4 mA
2.7
V
802 Vs()lo
Output Voltage Low
DVDD = 5 V, IOUT = -4 mA
DVDD = 3.3 V, IOUT = -4 mA
0.45
V
0.45
V
803 Idc()max Permissible Output DC Load
per pin
±10 mA
804 Idcmax
Permissible Total Output DC
Load
for all output pins in aggregate
±60 mA
805 tr()
Rise Time
806 tf()
Fall Time
807 fclk(SCL) SCL Clock Frequency
DVDD = 5 V, CL = 50 pF
DVDD = 3.3 V, CL = 50 pF
DVDD = 5 V, CL = 50 pF
DVDD = 3.3 V, CL = 50 pF
I2C access to EEPROM on power up
after configuration, max. at fosc = 32 MHz
50
ns
30
ns
50
ns
30
ns
100 kHz
fosc/128 250 kHz
808 twhi
Duty Cycle at OUTA, OUTB
referred to period T, see Fig. 2
50
%
809 tAB
Output Phase OUTA vs. OUTB referred to period T, see Fig. 2
25
%
810 tMTD
Minimum Edge Distance at
OUTA vs. OUTB
fcore = fxtl or fosc, AB_CFG1.div = 0,
AB_VTOP = 0, see Fig. 2
1/fcore