IC-NQ Datasheet, PDF (9/25 Pages) IC-Haus GmbH – 13-bit Sin/D CONVERTER WITH CALIBRATION

iC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 9/25
OPERATING REQUIREMENTS: BiSS and SSI Interface
Operating Conditions: VDD = 5 V ±10 %, Ta = -25 ... 85 °C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD
Item Symbol Parameter
Conditions
Fig.
No.
SSI Output (SELSSI = 1)
I001 T_MAS
Permissible Clock Period
CFGTOS = 0x01
4
I002 t_MASh
Clock Signal Hi Level Duration
4
I003 t_MASl
Clock Signal Lo Level Duration
4
BiSS Sensor Mode
I004 T_MAS
Permissible Clock Period
CFGTOR selected in accordance with 5
table on page 15
I005 t_MASh
Clock Signal Hi Level Duration
5
I006 t_MASl
Clock Signal Lo Level Duration
5
BiSS Register Mode
I007 T_MAR
Permissible Clock Period
CFGTOR selected in accordance with 6
table on page 15
I008 t_idle
Permissible Clock Halt (idle)
6
I009 t_MARh
Clock Signal Hi Level Duration
6
I010 t_MARh
Clock Signal Hi Level Duration
read out of register data
6
I011 t_MARl
Clock Signal Lo Level Duration
6
I012 t_MA0h
"Logic 0" Hi Level Duration
6
I013 t_MA1h
"Logic 1" Hi Level Duration
6
Min.
Unit
Max.
250
2x t_tos
ns
25
t_tos
ns
25
t_tos
ns
100
ns
25
t_tos
ns
25
ns
4
µs
0 indefinite
t_tor
ns
30
70
%
TMAR
t_tor
ns
10
30
%
TMAR
70
90
%
TMAR
Figure 4: Timing diagram of SSI output.
Figure 5: Timing diagram of BiSS sensor mode.
Figure 6: Timing diagram of BiSS register mode.