IC-NQ Datasheet, PDF (7/25 Pages) IC-Haus GmbH – 13-bit Sin/D CONVERTER WITH CALIBRATION

iC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 7/25
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated
Item Symbol Parameter
No.
Conditions
Zero Comparator
B01 Vos()
Input Offset Voltage
V() = Vcm()
B02 Iin()
Input Current
V() = 0 V ... VDDA
B03 Vcm()
Common-Mode Input Voltage
Range
B04 Vdm()
Differential Input Voltage Range
Incremental Outputs A, B, Z and BiSS Interface Output SLO
D01 Vs()hi
Saturation Voltage hi
Vs()hi = VDD - V(); I() = -4 mA
D02 Vs()lo
Saturation Voltage lo
I() = 4 mA
D03 tr()
Rise Time
CL() = 50 pF
D04 tf()
Fall Time
CL() = 50 pF
D05 RL()
Permissible Load at A, B
TMA = 1 (calibration mode)
BiSS Interface: Inputs MA, SLI
E01 Vt()hi
Threshold Voltage hi
E02 Vt()lo
Threshold Voltage lo
E03 Vt()hys Hysteresis
Vt()hys = Vt()hi - Vt()lo
E04 Ipu(MA) Pull-up Current in MA
V() = 0 ... VDD - 1 V
E05 Ipd(SLI) Pull-down Current in SLI
V() = 1 ... VDD
E06 fclk(MA)
Permissible Clock Frequency at SSI protocol
MA
BiSS B protocol: sensor mode
BiSS B protocol: register mode
E07 tp(MA-
SLO)
Propagation Delay: MA edge vs. all modes, RL(SLO) ≥ 1 kΩ
SLO output
E08 tbusy()s Processing Time Sensor Mode delay of start bit
E09 tbusy()r Processing Time Register Mode delay of start bit with read access to EEPROM
E10 tidle()
Interface Blocking Time
powering up with no EEPROM
EEPROM Interface, Control Logic: Inputs SDA, NERR
F01 Vt()hi
Threshold Voltage hi
F02 Vt()lo
Threshold Voltage lo
F03 Vt()hys Hysteresis
Vt()hys = Vt()hi - Vt()lo
F04 tbusy()cfg Duration of Startup Configuration error free EEPROM access
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR
G01 f()
Write/Read Clock at SCL
G02 Vs()lo
Saturation Voltage lo
I() = 4 mA
G03 Ipu()
Pull-up Current
V() = 0 ... VDD - 1 V
G04 ft()
Fall Time
CL() = 50 pF
G05 tmin()lo
G06 Tpwm()
Error Signal Indication Time at MA = hi, no BiSS access, amplitude or frequeny
NERR (lo signal)
error
Error Signal PWM Cycle Duration fosc() subdivided 2²²
at NERR
G07 RL()
Permissible Load at SDA, SCL TMA = 1 (calibration mode)
Min.
-20
-50
1.4
0
1
0.8
300
-240
20
10
0
0.8
300
-600
10
1
Unit
Typ. Max.
20
mV
50
nA
VDDA- V
1.5
VDDA V
0.4
V
0.4
V
60
ns
60
ns
MΩ
2
V
V
mV
-120 -25
µA
120 300 µA
4
MHz
10 MHz
0.25 MHz
50
ns
0
0
2
ms
1
1.5
ms
2
V
V
mV
5
7
ms
20 100 kHz
0.45
V
-300 -75
µA
60
ns
ms
60.7
ms
MΩ