IC-NQ Datasheet, PDF (19/25 Pages) IC-Haus GmbH – 13-bit Sin/D CONVERTER WITH CALIBRATION

iC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
BiSS INTERFACE
Rev D1, Page 19/25
Serial BiSS communication differentiates between the
fast cyclic transmission of sensor data for the output of
angle position and period counter data and the trans-
mission of register data which can include bidirectional
read and write access.
The required mode of communication is initiated by the
interface master; as a slave iC-NQ determines up to
which maximum clock interval the selected mode is re-
tained. Sensor mode timeout t_tos and register mode
timeout t_tor thus give the master a minimum clock fre-
quency of fclk(MA)min.
Protocol and Data Format
CFGTOS
Code
0x00
0x01
0x02
0x03
CFGTOR
Code
0x00
0x01
0x02
0x03
Notes
Adr 0x06, Bit 5:4
Timeout t_tos Ref. clock
Sensor mode counts
fclk(MA) min*
typ. 128 µs
256-259
11 kHz
typ. 16 µs
32-35
88 kHz
typ. 4 µs
8-11
352 kHz
typ. 1 µs
2-5
1.41 MHz
Adr 0x06, Bit 7:6
Timeout t_tor
Ref. clock
Regist. mode counts
fclk(MA) min*
typ. 1 ms
2049-2060
1.4 kHz
typ. 256 µs
513-514
5.5 kHz
typ. 32 µs
67-68
42 kHz
not permitted –
–
A
ref.
clock
count
is
equal
to
32
fosc
(see
El.
Char.
A01 ). The permissible max. clock frequency is
specified by item E06 .
Table 31: Interface Timeouts
M2S
Code
0x00
0x01
0x00
0x01
0x02
0x03
Notes
Adr 0x00, Bit 6:5
SCD
MCD
SCD*
CRC Poly.
not in use
Chip releases iC-NQ X2, iC-NQ X3:
-
0x25
1 zero bit
P(7:0)
0x25
1 zero bit
Chip release iC-NQ V2:
-
0x25
1 zero bit
P(7:0)
0x25
1 zero bit
P(11:0)
0x43
1 zero bit
P(23:0)
0x43
n/a
*) Period counter output via SCD
Table 32: Period Counter Output
BiSSMOD
Code
0x00
0x01
Adr 0x00, Bit 7
Version
Description
B
BiSS B without multicycle data
C
Transparency for BiSS C
Table 33: Protocol Version
Figure 18: BiSS B Protocol
Single-Cycle Data Channel: SCD
Bits
Type
Label
0, 8
DATA
Period Counter P(7:0)
0,8, 12, 24*
Period Counter P(23:0)*
(multiturn position)
3...13
DATA
Angle Data S(12:0):
3 to 13 bits (singleturn position)
1
ERROR Error bit E1 (amplitude error)
1
ERROR Error bit E0 (frequency error)
5
CRC
Polynomial 0x25
x⁵ + x² + x⁰ (inverted bit output)
6*
CRC
Polynomial 0x43*
x⁶ + x¹ + x⁰ (inverted bit output)
Multicycle Data Channel: MCD - not in use
Bits
Type
Label
1
zero bit
Register Data Channel: CD
Bits
Type
Label
3
ID
Slave ID
7
ADR
Register Address
1
WNR
Write-Not-Read Command
4
CRC
Polynomial 0x13
x⁴ + x¹ + x⁰ (inverted bit output)
Adr
Content
8
0x10.. 1F Device Configuration Data
0x20.. 77 OEM Daten
0x78.. 7F BiSS Identifier
4
CRC
Polynomial 0x13
x⁴ + x¹ + x⁰ (inverted bit Output)
Table 34: BiSS Data Channels
*) For chip release iC-NQ V2