IC-MQ_15 Datasheet, PDF (7/43 Pages) IC-Haus GmbH – Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev F3, Page 7/43
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 °C...125 °C, IBN calibrated to 200 µA, unless otherwise stated
Item Symbol Parameter
No.
Conditions
Unit
Min. Typ. Max.
117 PHI12
Phase Error Calibration Range CH1 vs. CH2
±20.2
°
118 ∆PHI12 Phase Error Calibration Step
Width
0.63
°
119 INL(PHI12) Integral Linearity Error of Phase limited test coverage (guaranteed by design)
-0.8
Calibration
120 fin()
Permissible Maximum Input Freq. analog signal path;
200
with interpolation of x1, x2
500
0.8
°
kHz
kHz
121 Vout(X2) Output Voltage at X2
BIASEX = 10, I(X2) = 0, referenced to VRE-
Fin12
95 100 105
%
122 Vin(X2)
Permissible Input Voltage Range BIASEX = 11
at X2
0.5
VDDS V
−2
123 Rin(X2) Input Resistance at X2
BIASEX = 11, RIN0(3:0) = 0x01, RIN12(3:0) = 20
27
35
kΩ
0x01
Sine-To-Digital Conversion
201 AAabs Absolute Angle Accuracy
referenced to 360° input signal, ideal waveform,
quasi static signals, adjusted signal condition-
ing, SELHYS = 0
0.9 1.8
°
202 AArel
Relative Angle Accuracy
referenced to output period T (see Fig. 1), ideal
waveform, quasi static signals;
at 4 edges per period
at 100 edges per period
at 384 edges per period
at 400 edges per period
10
%
<0.5 10
%
10
%
<2
10
%
203 AAR
Repeatability
Line Driver Outputs PA, NA, PB, NB, PZ, NZ
see 201; VDD = const., T_j = const.
0.1
°
501 Vs()hi
Saturation Voltage hi
Vs()hi = VDD - V();
SIK(1:0) = 00, I() = -1.2 mA
SIK(1:0) = 01, I() = -4 mA
SIK(1:0) = 10, I() = -20 mA
SIK(1:0) = 11, I() = -50 mA
200 mV
200 mV
400 mV
700 mV
502 Vs()lo
Saturation Voltage lo
SIK(1:0) = 00, I() = 1.2 mA
SIK(1:0) = 01, I() = 4 mA
SIK(1:0) = 10, I() = 20 mA
SIK(1:0) = 11, I() = 50 mA
200 mV
200 mV
400 mV
700 mV
503 Isc()hi
Short-Circuit Current hi
V() = 0 V;
SIK(1:0) = 00
SIK(1:0) = 01
SIK(1:0) = 10
SIK(1:0) = 11
-4
-12
-60
-150
-1.2 mA
-4
mA
-20 mA
-50 mA
504 Isc()lo
Short-Circuit Current lo
V() = VDD;
SIK(1:0) = 00
SIK(1:0) = 01
SIK(1:0) = 10
SIK(1:0) = 11
1.2
4
mA
4
12
mA
20
60
mA
50
150 mA
505 tr()
Rise Time
RL = 100 Ω to GND;
SSR(1:0) = 00
SSR(1:0) = 01
SSR(1:0) = 10
SSR(1:0) = 11
5
20
ns
5
40
ns
20
140
ns
50
350
ns
506 tf()
Fall Time
RL = 100 Ω to VDD;
SSR(1:0) = 00
SSR(1:0) = 01
SSR(1:0) = 10
SSR(1:0) = 11
5
20
ns
5
40
ns
30
140
ns
50
350
ns
507 Ilk()tri
Leakage Current
TRIHL(1:0) = 11 (tristate)
20 100 µA
508 IIk()rev Leakage Current
reversed supply voltage
100
µA
509 Rin()cal Test Signal Source Impedance Op. modes Calibration 1, 2, 3
2.5
4
kΩ
510 I()cal
Permissible Test Signal Load Op. modes Calibration 1, 2, 3
-3
3
µA