IC-MQ_15 Datasheet, PDF (17/43 Pages) IC-Haus GmbH – Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
OPERATING MODES
Rev F3, Page 17/43
iC-MQ has various modes of operation, for which the
functions of outputs PA, NA, PB, NB, PZ, NZ and ERR
are altered.
ture signal with a zero pulse. Only in these modes
are the line drivers and the reverse polarity protection
feature active.
Two operating modes can be selected for the output of
the angle position in normal operation. Mode 191/193
provides control signals for devices compatible with
74HC191 or 74HC193, whereas in Mode ABZ the angle
position is output incrementally as an encoder quadra-
In order to condition the input signals and to cali-
brate and test iC-MQ Calibration and Test modes are
available. Digital and analog test signals are pro-
vided; the latter must always be measured at high load
impedance.
MODE(3:0)
Code
0x00
0x0F
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Operating Mode
Mode ABZ
Mode 191/193
Calibration 1
Calibration 2
Test 3*
Test 4*
Test 5*
Test 6*
Calibration 3
Lo-Signal
Hi-Signal
Test 10*
System Test*
Test 12*
—
IDDQ Test*
Hints
Addr. 0x02; bit 3:0
Pin PA
Pin NA
Pin PB
Pin NB
Pin PZ
Pin NZ
A
not(A)
B
not(B)
Z
not(Z)
CPD
CPU
CP
nU/D
MR
nPL
TANAZ(2) VREFIZ
VREFISC IBN
PCH0
NCH0
PCH1
NCH1
PCH2
NCH2
VDC1
VDC2
VPAH
VPD
—
CGUCK IPF
V05
PS_out
NS_out
PC_out
NC_out
PZO
NZO
PSIN
NSIN
PCOS
NCOS
PZO
NZO
PCH1i
NCH1i
PCH2i
NCH2i
VDC1
VDC2
VTs
VTth
—
—
VTTFE
VTTSE
All outputs and SCL, SDA, ERR to low level
All outputs to high level
TP
CLK6
CLK1
CLK3/8
Z_In
CLK4
A₄
A₈
B₄
B₈
Z_In
TP1
A
not(A)
B
not(B)
Z
not(Z)
—
—
—
—
—
—
All PU/PD resistors, oscillator and analog supply voltage deactivated.
*) Test function for iC-Haus device test only. **) EMTD = 0x00, EMASKA = 0x10
Pin ERR
ERR / Zin**
ERR
IERR
IERR
IERR
IERR
res.
ERR
ERR
ERR
—
Table 13: Operating Modes
Mode ABZ
In Mode ABZ A/B signals are generated and output
via PA, NA, PB and NB. A freely configurable zero sig-
nal is simultaneously provided at pins PZ and NZ. The
differential RS422 line drivers are active; an Nx pin con-
stantly supplies a complementary signal which is the
inversion of pin Px.
Mode 191/193
In Mode 191/193 the output pins provide control sig-
nals for counter devices compatible with 74HC191 or
74HC193 according to the following table. The driving
capability (SIK) and the slew rate (SSR) of the output
drivers must be selected so that the clock pulses can be
output with a low pulse of typically 110 ns (see Electrical
Characteristics 511).
Mode 191/193
Pin Signal
PA CPD
NA CPU
PB CP
NB nU/D
PZ MR
NZ nPL
Description
Clock Down Pulse
Clock Up Pulse
Clock Pulse
Count Direction (0: up, 1: down)
Asynch. Master Reset (active high)
Signal is ’1’ if index position is reached,
otherwise ’0’.
Asynch. Parallel Load Input (active low) /
Reset (active low)
Signal is ’0’ if index position is reached,
otherwise ’1’.
Table 14: Operating mode for counter devices compati-
ble with 74HC191 or 74HC193.