IC-MQ_15 Datasheet, PDF (15/43 Pages) IC-Haus GmbH – Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev F3, Page 15/43
I²C Slave Mode (ENSL = 1)
In this mode iC-MQ behaves like an I²C slave with the
device ID 0x55 and the configuration interface permits
write and read accesses to iC-MQ’s internal registers.
For chip release verification purposes an identification
value is stored under ROM address 0x2F; a write ac-
cess to this address is not permitted.
CHPREL
Code
0x00
0x04
0x08
0x09
Addr 0x2F, bit 7:0 (ROM)
Chip Release
Not available
iC-MQ 3
iC-MQ X
iC-MQ X1
Table 7: Chip Release
END
Code
0
1
Notes
Addr 0x02, bit 7
Function
Standby: Sin/D converter and line driver disabled
(configuration changes allowed, see Table 10)
Enable Device: Restart of Sin/D conversion, line
driver active (configuration data must be valid)
END is evaluated only during I²C slave mode.
Write access changes the function.
Read access does not return the chip’s state.
Program END = 1 to EEPROM.
Table 8: Enable Device
The registers 0x0 to 0x2E must be initialized with cor-
rect values before enabling iC-MQ. This can be done
through the I²C slave interface if iC-MQ is used without
EEPROM or if the EEPROM content is invalid. Initially,
END (bit 7 of address 0x02) must be set to zero, then
all registers must be configured. Finally, set END to one
without changing other bits of address 0x02 to enable
the device.
Addr 0x02
bit 7 = 0
END = 0
Write registers
0x00 ... 0x2E
Configuration
Addr 0x02
bit 7 = 1
END = 1
Figure 2: Programming via I²C. END is altered by
changing only bit 7 of address 0x02 and
leaving bits 6:0 unchanged.
Intermediate error information buffer
(Addr. 0x40-0x43)
The intermediate error information buffer is initialized
whenever iC-MQ is enabled (END set to 1): ERR1 and
ERR3 data is copied from RAM Addr. 0x30-0x33, and
ERR2 data is initialized with 0.
The intermediate error information is modified based
on EMASKE and occurring errors. (See section Error
Logging on page 31.)
The data of the intermediate error information buffer
is invalid after an EEPROM write access failed. In
this case END must be toggled (set to 0, then set to
1) before accessing the intermediate error information
buffer.
Register
RAM Addr
0x00-0x21
0x22-0x2A
0x2B-0x2E
0x2F
0x30-0x33
0x34-0x3A
0x3B-0x3E
0x3F
0x40-0x43
0x44-0x7F
Note
Read access via I²C slave mode (ENSL = 1)
Content
Configuration data
(see EEPROM addresses 0x00-0x21)
Not available*
OEM data (4 byte)
(see EEPROM addresses 0x2B-0x2E)
Chip release CHPREL(7:0)
Configuration data
(see EEPROM addresses 0x30-0x33)
Not available
OEM data (4 byte)
(see EEPROM addresses 0x2B-0x2E)
Chip release CHPREL(7:0)
Intermediate error information buffer
Not available
*) The EEPROM addresses 0x22-0x2A (OEM data)
are not available in iC-MQ’s RAM.
Table 9: RAM Read Access
Register
RAM Addr
0x00
0x01
0x02
0x03-0x16
0x17
0x18-0x21
0x2B-0x2E
0x2F
0x30-0x33
0x34-0x43
0x44-0x7F
Write access via I²C slave mode (ENSL = 1)
Access and conditions
Changes permitted during standby (END = 0)
Changes permitted
(wrong entries for CFGIBN can limit functions)
Changes to bits 6:0 are permitted only during
standby (END = 0, ie. bit 7);
Restarting Sin/D conversion by changing END (bit 7)
is permitted only with no changes of operating mode
(bits 6:0 remain as set)
Changes permitted, no restrictions
Changes to bits 7:4 and 2:0 are permitted during
standby (END = 0)
(ENSL, bit 3 must be kept 1)
Changes permitted during standby (END = 0)
Changes permitted, no restrictions
No write access permitted
Changes permitted during standby (END = 0)
No write access permitted
Not available
Table 10: RAM Write Access