IC-HT_15 Datasheet, PDF (41/45 Pages) IC-Haus GmbH – DUAL CW LASER DIODE DRIVER

iC-HT
DUAL CW LASER DIODE DRIVER
preliminary
Channel 1 configuration registers
EACC1
0
1
Addr. 0x10; bit 0
R/W 0
APC mode enabled for channel 1 (light power
regulation)
ACC mode enabled for channel 1 (laser current
regulation)
Table 92: Enable APC/ACC channel 1
ECIE1
0
1
Addr. 0x10; bit 1
R/W 0
External CI capacitor for channel 1 disconnected
External CI capacitor for channel 1 connected
Table 93: Enable external CI capacitor channel 1
RMD1
0x00
...
0xFF
Rev B1, Page 41/45
Addr. 0x12; bit 7:0
R/W 0xFF
PLR1 set to the minimum resistance
PLR1 resistor set to
Rmd
=
Rmd₀(1
+
∆
Rmd (%)
100
)ⁿ
+1_,
n
from
0
to
255
PLR1 resistor set to the maximum resistance
Table 99: MDA resistor channel 1
COMP1
000
...
111
Addr. 0x13; bit 6:4
R/W 011
Minimum regulator delay compensation
for channel 1, slower response
Maximum regulator delay compensation
for channel 1, faster response
Table 100: Regulator delay compensation channel 1
DISP1
0
1
Addr. 0x10; bit 2
PLR enabled for channel 1
PLR disabled for channel 1
Table 94: Disable PLR channel 1
R/W 0
DISC1
0
1
Addr. 0x10; bit 3
Channel 1 can be enabled by EC1 pin
Channel 1 cannot be enabled by EC1 pin
R/W 1
Table 95: Disable channel 1
EOC1
0
1
Addr. 0x10; bit 4
R/W 1
Channel 1 regulator offset compensation disabled
Channel 1 regulator offset compensation enabled
Table 96: Enable offset compensation channel 1
RLDKS1
00
01
10
11
Addr. 0x13; bit 3:2
R/W 00
V(LDK1) < 0.5 V sets the LDKSAT1 alarm bit
V(LDK1) < 0.8 V sets the LDKSAT1 alarm bit
V(LDK1) < 1.0 V sets the LDKSAT1 alarm bit
V(LDK1) < 1.2 V sets the LDKSAT1 alarm bit
Table 101: LDK saturation threshold selection chan-
nel 1
REF1
0x000
...
0x3FF
Addr. 0x13/14; bit 9:0
R/W 0x000
Channel 1 regulator reference voltage set to
minimum voltage
Channel 1 regulator reference voltage set to
Vref
=
Vref₀(1
+
∆
Vref (%)
100
)ⁿ
+
1
,
n
from
0
to
1023
Channel 1 regulator reference voltage set to
maximum voltage
Table 102: Regulator voltage reference channel 1
ADCC1(2:0)
Addr. 0x10; bit 7:5
R/W 000
0xx
Channel 1 ADC disabled
100
Channel 1 ADC sourced by V(MDA1), ADSNF1 = 0
100
Channel 1 ADC sourced by V(PLR1), ADSNF1 = 1
101
Channel 1 ADC sourced by V(VB)
110
Channel 1 ADC sourced by V(VDD)
111
Channel 1 ADC sourced by V(LDK1)
Table 97: ADC source selection channel 1
ILIM1
0x0A
...
0xFF
Addr. 0x11; bit 7:0
R/W 0xFF
Channel 1 overcurrent threshold set to the
minimum current
Channel 1 overcurrent threshold set to
Ilim = (∆ I(LDK ) · n), n from 10 to 255
Channel 1 overcurrent threshold set to the
maximum current
Table 98: Overcurrent threshold configuration chan-
nel 1
RACC1
0
1
Addr. 0x1A; bit 0
Current range high for channel 1
Current range low for channel 1
R/W 0
Table 103: Current range configuration channel 1
ADSNF1
0
1
Addr. 0x1A; bit 2
ADC measurement MDA1 pad (force)
ADC measurement PLR1 (sense)
R/W 0
Table 104: ADC channel 1 sense/force selection