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IC-HT_15 Datasheet, PDF (34/45 Pages) IC-Haus GmbH – DUAL CW LASER DIODE DRIVER | |||
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iC-HT
DUAL CW LASER DIODE DRIVER
preliminary
DIGITAL INTERFACE AND MEMORY INTEGRITY MONITOR
Rev B1, Page 34/45
iC-HT provides a microcontroller slave interface by se-
lection on the EMC pin. iC-HT support the interfaces
SPI or I2C that are selected by the INS/WKR pin.
ent registers) to be made prior to apply it to the laser
channels. iC-HT has two different modes selectable by
the MODE(1:0) register (address 0x1C).
EMC
lo
Open
hi
Addr. Pin;
iC-WK-mode, digital interfaces disabled
Not allowed, error signaled
MCU mode, interface selected by INS/WKR
enabled
Table 67: Enable microcontroller
INS/WKR
lo
Open
hi
Addr. Pin;
SPI interface selected
Not allowed, error signaled.
I2C interface selected
Table 68: Interface selection I2C or SPI
MODE(1:0)
Addr. 0x1C; bit 1:0
00
Invalid parameter
01
Operation mode
10
Conï¬guration mode
11
Invalid parameter
R/W 01
Table 69: Conï¬guration and operation mode
In Conï¬guration mode, the conï¬guration memory
(address 0x10 to 0x1F) can be written and read back
to check a correct communication without changing the
present conï¬gured operation state of the iC-HT. In this
mode, the memory integrity check is disabled.
The conï¬guration memory is integrity monitored and
atomic executable (all at once: changes of the conï¬g-
urations without any direct effects, the changes are ex-
ecuted at once by command ) to the functional blocks
of iC-HT.
Integrity monitoring is implemented by a duplication of
the conï¬guration registers into a validation page (see
description below) where the register are automatically
copied with inverted value. Every register bit is com-
pared with its validation copy and in case of difference,
a memory error is generated and both laser channels
are switched off.
Atomic appliance is achieved by latching the conï¬gu-
ration registers. This permits a full conï¬guration (differ-
iC-HT will monitor the time elapsed in conï¬guration
mode and automatically switch the laser off if it ex-
ceeds a conï¬guration mode timeout. The time in con-
ï¬guration mode must less than 40 ms for ensuring that
no conï¬guration timeout occurs during conï¬guration
(cf. Electrical Characteristics No. E02). The timeout
can be up to 164 ms.
When writing the conï¬guration is completed, iC-HT is
switched to operation mode by writing "10" into the
MODE register (address 0x1C). In operation mode
the conï¬guration is applied to the iC-HT and the mem-
ory integrity check activated. In this mode conï¬gura-
tion registers can only be read (except MODE(1:0) reg-
ister, which is always accessible). Figure 21 shows the
interface to memory structure.
CFG(127:0)
0x10
0x1F
RAM
MODE
Addr. 0x1C
LATCH
MEMERR
ERROR
CHECK
0x30
0x3F
VALIDATION
DB(7:0)
SPI / I2C
RNW
ADR(6:0)
Addr.
Decoder
RNW_RAM
RNW_VAL
Figure 21: Interface, RAM integrity monitoring and conï¬guration latching
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