IC-MA3 Datasheet, PDF (16/19 Pages) IC-Haus GmbH – ANGULAR HALL SENSOR

iC-MA3 ANGULAR HALL SENSOR
WITH SIN/COS OUTPUT, CASCADABLE
Rev A2, Page 16/19
Signal examples for output GAIN
For the following examples we assume iC-MA3 is
configured for single-chip operation, single-ended and
mid-level output: signal GAIN is output at P3.
Example 1: Gain at 50 % of maximum
At VDD = 5.0 V, the output reference Vref is 2.5 V.
Due to mid-level output, 500 mV is the maximum signal
level that can be reached at P3.
In this case, the voltage at pin GAIN is:
V(GAIN) = 0.5 x Vout(GAIN)fs
approx. 0.5 x 2.5 V = 1.25 V
And at pin P3, the max. voltage is:
V(P3) = Vref + 0.5 x Vout()pk
approx. 2.5 V + 0.5 x 500 mV = 2.75 V.
At VDD = 3.3 V we obtain:
V(GAIN) approx. 1.25 V
V(P3) approx. 1.65 V + 0.5 x 500 mV = 1.9 V
due to a lower Vref.
Example 2: Gain at maximum (insuffient field strength)
At VDD = 5.0 V, the output reference Vref is 2.5 V.
Due to mid-level output, 500 mV is the maximum signal
level that can be reached at P3.
In this case, the voltage at pin GAIN is:
V(GAIN) = Vout(GAIN)fs, approx. 2.5 V
And at pin P3, the voltage is:
V(P3) = Vref + Vout()pk
approx. 2.5 V + 500 mV = 3.0 V.
At VDD = 3.3 V we obtain:
V(GAIN) approx. 2.5 V
V(P3) approx. 1.65 V + 500 mV = 2.15 V
due to a lower Vref.
Monitoring by output NERR
After enabling the IC, the amplitude control needs time
for settling (ts()ctrl), for the adaption to the external field
strength and to get to the preset output level. During
this phase, the low-active error output NERR shows a
low signal, indicating that the output amplitude is poor
and may not allow accurate measurements. The error
output NERR releases to high, as soon as the con-
trolled amplitude has reached approx. 80 %. of the
preset level.
Any insufficient field strength, a loss-of-magnet condi-
tion for instance, leads to amplitude control saturation
at maximum gain. If the output amplitude does not keep
approx. 80% of the preset level, error outout NERR
indicates a low.
STEP-UP CONVERTER
The built-in step-up converter supplies certain inter-
nal circuit sections, which benefit from a higher supply
voltage. To further stabilize this internally used supply
voltage, and to prevent it from impact of disturbances,
an additional external capacitor may be connected at
pin VDDS versus pin GND.
Note: When iC-MA3 is powered up, any capacitor at
VDDS slows down the ramp-up of the step-up voltage,
and so the signal output experiences a delay. Thus,
for the selection of the capacitor value, the startup-time
required by the application may need to be considered.
Mode
CVDDS
Single-chip operation 1 . . . 100nF
Chain operation
approx. 1nF
Table 11: Recommended bypass capacitor at VDDS vs.
GND