IC-MA3 Datasheet, PDF (13/19 Pages) IC-Haus GmbH – ANGULAR HALL SENSOR

iC-MA3 ANGULAR HALL SENSOR
WITH SIN/COS OUTPUT, CASCADABLE
Rev A2, Page 13/19
CLK
NEN(0)
NEN(1)
tp(VDD)on
NEN(2)
NEN(3)
P1
High-Z
P2
High-Z
GAIN High-Z
NERR High-Z
PSIN(0)
PCOS(0)
GAIN(0)
ts()ctrl
iC-MA3 #0 active
VREF(0)
GAIN(0)
tp(VDD)on
High-Z
High-Z
High-Z
High-Z
PSIN(1)
PCOS(1)
GAIN(1)
ts()ctrl
iC-MA3 #1 active
VREF(1)
GAIN(1)
tp(VDD)on
High-Z
High-Z
High-Z
High-Z
PSIN(2)
PCOS(2)
GAIN(2)
ts()ctrl
iC-MA3 #2 active
VREF(2)
GAIN(2)
Figure 7: Line signals and timing for chain operation (example for single-ended output)
High-Z
High-Z
High-Z
High-Z
Line timing
A settling time ts()ctrl is required for the adaption to the
magnet field strength and its processing. Only after this
initial settling the first values (here PSIN and PCOS)
can be read correctly. As there is no further settling
required for the second cycle, reading and evaluating
the second values (here VREF and GAIN) can follow
quicker.
For chain operation, the following procedure is recom-
mended:
1. Set CLK to low, then activate the chain with
NEN(0) = low.
2. After the activation of the chain, wait at least
tp(VDD)on, then set CLK = high.
After enabling an IC, the bus outputs are activated with
the first rising edge of the CLK signal. Note that also
the analog bus lines need to settle following output acti-
vation. Thus, the accuracy of the measurement signals
can be improved if the outputs are activated early, soon
after enabling a device (by setting CLK high).
Note that the operation mode has to be read after IC
activation (by NEN = low), so that the power-on proga-
tion delay tp(VDD)on must be passed before an IC is
able to react on the signal at input CLK.
3. Wait at least until NERR changes from low to high
before reading the first values of IC #0.
4. With the second rising edge of CLK, the second
values of IC #0 are available on the bus lines,
which can be directly read.
5. The second falling edge of CLK causes the acti-
vation of IC #1 by NEN(1).
6. After the activation of IC #1, wait at least for
tp(VDD)on again, before setting CLK = high.
The sequence described in steps 3 through 6 repeats
until the end of the chain is reached and a new measure-
ment cycle is started by resetting the chain (NEN(0) =
high).