HYMD264M726A8-J Datasheet, PDF (9/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM with PLL

HYMD264M726A(L)8-J/M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
<DDR333, DDR266(2-2-2)>
Parameter
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Write Recovery Time
Write to Read Command Delay
Auto Precharge Write Recovery + Precharge Time
System Clock Cycle Time
CL = 2.5
CL = 2
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
Clock Half Period
Data Hold Skew Factor
Valid Data Output Window
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Input Pulse Width
Write DQS High Level Width
Symbol
DDR333
Min
Max
tRC
60
-
tRFC
72
-
tRAS
42
70K
tRAP
18
-
tRCD
18
-
tRRD
12
-
tCCD
1
-
tRP
18
-
tWR
15
-
tWTR
1
-
(tWR/tCK)
tDAL
+
-
(tRP/tCK)
6
12
tCK
7.5
12
tCH
0.45
0.55
tCL
0.45
0.55
tAC
-0.7
0.7
tDQSCK
-0.6
0.6
tDQSQ
-
0.45
tQH
tHP
-tQHS
-
tHP
min
(tCL,tCH)
-
tQHS
-
0.55
tDV
tQH-tDQSQ
tHZ
-0.7
0.7
tLZ
-0.7
0.7
tIS
0.75
-
tIH
0.75
-
tIS
0.8
-
tIH
0.8
-
tIPW
2.2
tDQSH
0.35
-
DDR266(2-2-2)
Min
Max
60
-
75
-
45
120K
15
-
15
-
15
-
1
-
15
-
15
-
1
-
(tWR/tCK)
+
-
(tRP/tCK)
7.5
12
7.5
12
0.45
0.55
0.45
0.55
-0.75
0.75
-0.75
0.75
-
0.5
tHP
-tQHS
-
min
(tCL,tCH)
-
-
0.75
tQH-tDQSQ
-0.75
0.75
-0.75
0.75
0.9
-
0.9
-
1.0
-
1.0
-
2.2
0.35
-
Unit
ns
ns
ns
ns
ns
ns
CK
ns
ns
CK
CK
ns
ns
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
Note
16
15
1, 10
1,9
10
17
17
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
6
Rev. 0.1/Apr. 02
9