HYMD264M726A8-J Datasheet, PDF (6/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM with PLL

CAPACITANCE (TA=25^oC, f=100MHz )
HYMD264M726A(L)8-J/M/K/H/L
Parameter
Pin
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Data Input / Output Capacitance
Data Input / Output Capacitance
A0 ~ A12, BA0, BA1
/RAS, /CAS, /WE
CKE0, CKE1
/S0, /S1
CK0, /CK0
DM0 ~ DM8
DQ0 ~ DQ63, DQS0 ~ DQS8
CB0 ~ CB7
Symbol Min
CIN1
95
CIN2
95
CIN3
65
CIN4
60
CIN5
30
CIN6
12
CIO1
12
CIO2
12
Max
110
110
80
75
45
18
18
18
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Output
VTT
RT=50Ω
Zo=50Ω
CL=30pF
VREF
Rev. 0.1/Apr. 02
6