HYMD264M726A8-J Datasheet, PDF (8/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM with PLL

HYMD264M726A(L)8-J/M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter Symbol
Test Condition
Speed
Unit Note
-J -M -K -H -L
Operating Current
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
IDD0 DQS inputs changing twice per clock cycle 1485 1485 1305 1305 1260 mA 1
; address and control inputs changing once
per clock cycle
Operating Current
One bank; Active - Read - Precharge; Burst
IDD1
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
1890 1890 1620 1620 1530
mA
1
per clock cycle
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down - mode;
CKE=Low, tCK=tCK(min)
360
mA 1
/CS=High, All banks idle; tCK=tCK(min);
Idle Standby Current
IDD2F
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF
900
900
720
720
630
mA
1
for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
450
mA 1
Active Standby
Current
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max);
IDD3N
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address
1080 1080 900 900 900 mA
1
and other control inputs changing once per
clock cycle
Burst=2; Reads; Continuous burst; One
Operating Current
IDD4R
bank active; Address and control inputs
changing once per clock cycle;
3150 3150 2700 2700 2160
1
tCK=tCK(min); IOUT=0mA
Operating Current
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
IDD4W changing once per clock cycle;
3150 3150 2700 2700 2160 ^mA
1
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at
Auto Refresh Current IDD5 100Mhz, 10*tCK for DDR266A & DDR266B 2610 2610 2340 2340 2205
1
at 133Mhz; distributed refresh
Self Refresh Current
IDD6
CKE=<0.2V; External clock
on; tCK =tCK(min)
Normal
Low Power
54
27
mA 1
mA 1
Operating Current -
Four Bank Operation
Four bank interleaving with BL=4 Refer to
IDD7 the following page for detailed test
3375 3375 3195 3195 2970 mA
condition
1
Note :
1. IDD Value doesn’t contain PLL Power.
Rev. 0.1/Apr. 02
8