HYMD264M726A8-J Datasheet, PDF (12/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM with PLL

HYMD264M726A(L)8-J/M/K/H/L
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Parameter
Symbol
Write DQS Low Level Width
tDQSL
Clock to First Rising edge of DQS-In
tDQSS
Data-In Setup Time to DQS-In (DQ & DM)
tDS
Data-in Hold Time to DQS-In (DQ & DM)
tDH
DQ & DM Input Pulse Width
tDIPW
Read DQS Preamble Time
tRPRE
Read DQS Postamble Time
tRPST
Write DQS Preamble Setup Time
tWPRES
Write DQS Preamble Hold Time
tWPREH
Write DQS Postamble Time
tWPST
Mode Register Set Delay
tMRD
Exit Self Refresh to Any Execute Command tXSC
Average Periodic Refresh Interval
tREFI
DDR266A
Min Max
0.35
-
0.75 1.25
0.45
-
0.45
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
15.6
DDR266B
Min Max
0.35
-
0.75 1.25
0.45
-
0.45
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
15.6
DDR200
Min Max
0.35
-
0.72 1.28
0.5
-
0.5
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
15.6
Unit Note
CK
CK
ns
6,7,
ns ^11~13
ns
CK
CK
CK
CK
CK
CK
CK
8
us
Rev. 0.1/Apr. 02
12