HY27UF082G2A Datasheet, PDF (9/45 Pages) Hynix Semiconductor – 2Gbit (256Mx8bit/128Mx16bit) NAND Flash

HY27UF(08/16)2G2A Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
Table 3: Address Cycle Map(x8)
NOTE:
1. L must be set to Low.
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
IO0
A0
A8
A11
A19
A27
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A9
A10
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
A12
A13
A14
A15
A16
A17
A20
A21
A22
A23
A24
A25
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
Table 4: Address Cycle Map(x16)
IO7
A7
L⁽¹⁾
A18
A26
L⁽¹⁾
IO8-IO15
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
L⁽¹⁾
NOTE:
1. L must be set to Low.
FUNCTION
READ 1
READ FOR COPY-BACK
READ ID
RESET
PAGE PROGRAM
COPY BACK PGM
BLOCK ERASE
READ STATUS REGISTER
CACHE PROGRAM
RANDOM DATA INPUT
RAMDOM DATA OUTPUT
CACHE READ START ⁽¹⁾
CACHE READ EXIT ⁽¹⁾
1st CYCLE 2nd CYCLE 3rd CYCLE
00h
30h
-
00h
35h
-
90h
-
-
FFh
-
-
80h
10h
-
85h
10h
-
60h
D0h
-
70h
-
-
80h
15h
-
85h
-
-
05h
E0h
-
00h
31h
-
34h
-
-
Table 5: Command Set
4th CYCLE
-
-
-
-
-
-
-
-
-
-
-
-
-
Acceptable command
during busy
Yes
Yes
NOTE:
1. Only for x8 product
Rev 0.4 / Mar. 2007
9