HY27UF082G2A Datasheet, PDF (22/45 Pages) Hynix Semiconductor – 2Gbit (256Mx8bit/128Mx16bit) NAND Flash

HY27UF(08/16)2G2A Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
Parameter
Symbol
3.3Volt
Min
Max
CLE Setup time
CLE Hold time
CE setup time
CE hold time
tCLS
15
tCLH
5
tCS
25
tCH
5
WE pulse width
ALE setup time
ALE hold time
Data setup time
Data hold time
Write Cycle time
WE High hold time
tWP
15
tALS
15
tALH
5
tDS
15
tDH
5
tWC
30
tWH
10
Address to Data Loading time
Data Transfer from Cell to register
ALE to RE Delay
tADL⁽²⁾
100
tR
20
tAR
15
CLE to RE Delay
Ready to RE Low
RE Pulse Width
WE High to Busy
Read Cycle Time
tCLR
15
tRR
20
tRP
15
tWB
100
tRC
30
RE Access Time
RE High to Output High Z
CE High to Output High Z
Cache Read RE high
RE High to Output hold
RE Low to Output hold
CE High to Output Hold
tREA
25
tRHZ
50
tCHZ
50
tCRRH
100
tRHOH
15
tRLOH
5
tCOH
15
RE High Hold Time
Output High Z to RE low
CE Access Time
WE High to RE low
tREH
10
tIR
0
tCEA
30
tWHR
60
Device Resetting Time (Read / Program / Erase)
tRST
5/10/500⁽¹⁾
Write Protection time
tWW⁽³⁾
100
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. tADL is the time from the WE rising edge of final address cycle to the WE rising of first data cycle.
3. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
Rev 0.4 / Mar. 2007
22