HY27UF082G2A Datasheet, PDF (14/45 Pages) Hynix Semiconductor – 2Gbit (256Mx8bit/128Mx16bit) NAND Flash

HY27UF(08/16)2G2A Series
2Gbit (256Mx8bit/128Mx16bit) NAND Flash
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operation is com-
pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the com-
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or
RE#, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple
memory connections even when R/B pins are common-wired. RE# or CE# does not need to be toggled for updated
status.
Refer to table 14 for specific Status Register definitions. The command register remains in Status Read mode until fur-
ther commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command
(00h) should be given before starting read cycles. See figure 9 for details of the Read Status operation.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Five read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd
cycle ID, 4th cycle ID, 5th cycle ID respectively. The command register remains in Read ID mode until further com-
mands are issued to it. Figure 18 shows the operation sequence, while tables 16 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased.
The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when
WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset
command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset com-
mand is written. Refer to figure 23.
Rev 0.4 / Mar. 2007
14