HYMD532M646CLP6-D43 Datasheet, PDF (8/20 Pages) Hynix Semiconductor – 200pin DDR SDRAM SO-DIMMs based on 512Mb C ver. (TSOP)

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200pin DDR SDRAM SO-DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
512MB, 64M x 64 Unbuffered DIMM: HYMD564M646C[L]P6
Symbol
Test Condition
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
CKE=<0.2V; External clock on; tCK Normal
=tCK(min)
Low Power
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
DDR400B
760
920
1080
1160
1280
1680
Speed
DDR333
720
840
80
280
360
480
1000
1080
1200
40
24
1640
DDR266B
Unit Note
640
mA
720
mA
mA
mA
mA
mA
920
mA
960
mA
1120
mA
mA
mA
1600
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 / Feb. 2006
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