HYMD532M646CLP6-D43 Datasheet, PDF (1/20 Pages) Hynix Semiconductor – 200pin DDR SDRAM SO-DIMMs based on 512Mb C ver. (TSOP)

200pin DDR SDRAM SO-DIMMs based on 512Mb C ver. (TSOP)
This Hynix unbuffered Small Outline, Dual In-Line Memory Module (DIMM) series consists of 512Mb C ver. DDR
SDRAMs in 400mil TSOP II packages on a 200pin glass-epoxy substrate. This Hynix 512Mb C ver. based unbuffered
SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is
suitable for easy interchange and addition.
FEATURES
• JEDEC Standard 200-pin small outline, dual in-line
memory module (SO-DIMM)
• Two ranks 64M x 64 organization
• 2.6V ± 0.1V VDD and VDDQ Power supply for
DDR400, 2.5V ± 0.2V for DDR333 and below
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock operations (CK & /CK) with
133/166/200MHz
• DLL aligns DQ and DQS transition with CK transition
• Programmable CAS Latency: DDR266(2, 2.5 clock),
DDR333(2.5 clock), DDR400(3 clock)
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Edge-aligned DQS with data outs and Center-aligned
DQS with data inputs
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial Presence Detect (SPD) with EEPROM
• Built with 512Mb DDR SDRAMs in 400 mil TSOP II
packages
• All lead-free products (RoHS compliant)
ADDRESS TABLE
Organization Ranks
256MB 32M x 64
1
512MB 64M x 64
2
SDRAMs
32Mb x 16
32Mb x 16
# of
DRAMs
4
8
# of row/bank/column Address
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
Refresh
Method
8K / 64ms
8K / 64ms
PERFORMANCE
Part-Number Suffix
Speed Bin
CL - tRCD- tRP
Max Clock
Frequency
CL=3
CL=2.5
CL=2
-D43¹
DDR400B
3-3-3
200
166
133
-J
DDR333
2.5-3-3
-
166
133
-H
Unit
DDR266B
-
2.5-3-3
CK
-
MHz
133
MHz
133
MHz
Note:
1. 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 and below
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.3 / Feb. 2006
1