HY64SD16162B Datasheet, PDF (8/11 Pages) Hynix Semiconductor – 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

HY64SD16162B Series
WRITE CYCLE 1 ( Note 1, 4, 5, 9, 10 ) ( /WE Controlled )
tWC
ADD
tCW
/CS1
tWR(2)
CS2
Vih
/UB, /LB
/WE
tAS
Data In
High-Z
Data Out
tAW
tBW
tWP
tWHZ(3,8)
tDW
Data Valid
tDH
tOW
(6)
(7)
WRITE CYCLE 2 ( Note 1, 4, 5, 9, 10 ) ( /CS1 Controlled )
tWC
ADD
tAS
tCW
/CS1
tWR(2)
CS2
Vih
tAW
tBW
/UB, /LB
/WE
Data In
High-Z
tWP
tDW
tDH
Data Valid
Data Out
High-Z
Notes :
1. A write occurs during the overlap of low /CS1, low /WE and low /UB and/or /LB.
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied.
4. If the /CS1, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. /OE is continuously low (/OE=VIL)
6. Q(data out) is the invalid data.
7. Q(data out) is the read data of the next address.
8. tWHZ is defined as the time at which the outputs achieve the high impedance state.
It is not referenced to output voltage levels.
9. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active.
10. Do not input data to the I/O pins while they are in the output state.
Revision 1.0 / December. 2002
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