HY64SD16162B Datasheet, PDF (5/11 Pages) Hynix Semiconductor – 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

HY64SD16162B Series
AC CHARACTERISTICS
Vdd=1.8V~2.2V, Vddq=1.7V~Vdd, TA= -25°C to 85°C(E) / -40°C to 85°C(I), unless otherwise specified
# Symbol
Parameter
-85
Min.
Max.
Unit
Read Cycle
1
tRC Read Cycle Time
85
-
ns
2
tAA Address Access Time
-
85
ns
3
tACS Chip Select Access Time
-
85
ns
4
tOE Output Enable to Output Valid
-
30
ns
5
tBA /LB, /UB Access Time
-
85
ns
6
tCLZ Chip Select to Output in Low Z
10
-
ns
7
tOLZ Output Enable to Output in Low Z
5
-
ns
8
tBLZ /LB, /UB Enable to Output in Low Z
10
-
ns
9
tCHZ Chip Disable to Output in High Z
0
10
ns
10
tOHZ Out Disable to Output in High Z
0
10
ns
11
tBHZ /LB, /UB Disable to Output in High Z
0
10
ns
12
tOH Output Hold from Address Change
5
-
ns
Write Cycle
13
tWC Write Cycle Time
85
-
ns
14
tCW Chip Selection to End of Write
70
-
ns
15
tAW Address Valid to End of Write
70
-
ns
16
tBW /LB, /UB Valid to End of Write
70
-
ns
17
tAS Address Set-up Time
0
-
ns
18
tWP Write Pulse Width
60
-
ns
19
tWR Write Recovery Time
0
-
ns
20
tWHZ Write to Output in High Z
0
10
ns
21
tDW Data to Write Time Overlap
30
-
ns
22
tDH Data Hold from Write Time
0
-
ns
23
tOW Output Active from End of Write
5
-
ns
AC TEST CONDITIONS
TA= -25°C to 85°C(E) / -40°C to 85°C(I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4 to Vddq*0.8
Input Rising and Fall Time
5ns
Input Timing Reference Level
0.9V
Output Timing Reference Level
0.5*Vddq
Output Load
See Below
AC TEST LOADS
D_OUT
Z0=50 Ohm
RL=50 Ohm
CL¹ =50 pF
VL=0.5*Vddq
Note
1. Including jig and scope capacitance.
Revision 1.0 / December. 2002
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