HY5756820C Datasheet, PDF (8/12 Pages) Hynix Semiconductor – 4 Banks x 8M x 8Bit Synchronous DRAM

HY57V56820C(L)T
AC CHARACTERISTICS II
Parameter
Symbol
-6
Min Max
-K
Min Max
-H
Min Max
-8
Min Max
-P
Min Max
-S
Min Max
Unit Note
RAS Cycle Time
Operation
Auto Refresh
tRC
tRRC
60
-
60
-
65
-
68
-
70
-
70
-
ns
60
-
60
-
65
-
68
-
70
-
70
-
ns
RAS to CAS Delay
tRCD
18
-
15
-
20
-
20
-
20
-
20
-
ns
RAS Active Time
tRAS
42 100K 45 100K 45 100K 48 100K 50 100K 50 100K ns
RAS Precharge Time
tRP
18
-
15
-
20
-
20
-
20
-
20
-
ns
RAS to RAS Bank Active Delay
tRRD
12
-
15
-
15
-
16
-
20
-
20
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
1
-
1
-
1
-
1
- CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
0
-
0
-
0
-
0
- CLK
Write Recovery Time
tWR
2
-
2
-
2
-
2
-
2
-
2
- CLK
Data-In to Active Command
tDAL
5
-
5
-
5
-
5
-
5
-
5
- CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
- CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
- CLK
MRS to New Command
tMRD
2
-
2
-
2
-
2
-
2
-
2
- CLK
Precharge to Data ^{CAS Latency = 3 tPROZ3}
3
-
3
-
3
-
3
-
3
-
3
- CLK
Output Hi-Z
CAS Latency = 2 tPROZ2
2
-
2
-
2
-
2
-
2
-
2
- CLK
Power Down Exit Time
tPDE
1
-
1
-
1
-
1
-
1
-
1
- CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
1
-
1
-
1
- CLK 1
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
-
64 ms
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.4 / July 2003
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