HY5756820C Datasheet, PDF (6/12 Pages) Hynix Semiconductor – 4 Banks x 8M x 8Bit Synchronous DRAM

HY57V56820C(L)T
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter
Symbol
Test Condition
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
Precharge Standby Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK = 15ns
IDD2PS CKE ≤ VIL(max), tCK = ∞
Precharge Standby Current
in Non Power Down Mode
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2NS ^{CKE ≥ VIH(min), tCK = ∞}
Input signals are stable.
Active Standby Current
in Power Down Mode
IDD3P CKE ≤ VIL(max), tCK = 15ns
IDD3PS CKE ≤ VIL(max), tCK = ∞
Active Standby Current
in Non Power Down Mode
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
Burst Mode Operating Current IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
CL=3
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
Speed
Unit Note
-6
-K -H -8 -P -S
130 120 120 120 110 100 mA
1
2.5
mA
2.0
35
mA
20
5.0
mA
5.0
45.0
mA
30.0
150 130 130 130 120 110 mA
1
220 220 220 200 200 200 mA
2
3
mA
3
1.5
mA
4
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V56820CT-6/K/H/8/P/S
4.HY57V56820CLT-6/K/H/8/P/S
Rev. 0.4 / July 2003
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