HY5756820C Datasheet, PDF (2/12 Pages) Hynix Semiconductor – 4 Banks x 8M x 8Bit Synchronous DRAM

PIN CONFIGURATION
VDD 1
DQ0 2
VDDQ 3
NC 4
DQ1 5
VSSQ 6
NC 7
DQ2 8
VDDQ 9
NC 10
DQ3 11
VSSQ 12
NC 13
VDD 14
NC 15
/WE 16
/CAS 17
/RAS 18
/CS 19
BA0 20
BA1 21
A10/AP 22
A0 23
A1 24
A2 25
A3 26
VDD 27
54
53
52
51
50
49
48
47
46
45
44
43
54pin TSOP II 42
400mil x 875mil 41
0.8mm pin pitch ₄₀
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
HY57V56820C(L)T
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A12
RAS, CAS, WE
DQM
DQ0 ~ DQ7
VDD/VSS
VDDQ/VSSQ
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.4 / July 2003
2