HY62V8100B Datasheet, PDF (7/12 Pages) Hynix Semiconductor – 128K x8 bit 3.3V Low Power CMOS slow SRAM

HY62V8100B Series
WRITE CYCLE 1(1,4,5,8) (/WE Controlled)
ADDR
/C S 1
tW C
tCW
tW R (2)
CS2
/W E
Data In
Data
Out
tAS
High-Z
tAW
tW H Z (3,7)
tW P
tDW
Data Valid
tDH
tOW
(5)
(6)
WRITE CYCLE 2 (Note 1,4,5,8) (/CS1, CS2 Controlled)
ADDR
/CS1
CS2
/W E
Data In
tAS
High-Z
tW C
tCW
tAW
tW R (2)
tW P
tDW
tDH
Data Valid
Data
Out
High-Z
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and a high CS2.
2. tWR is measured from the earlier of /CS1 or /WE going high or CS2 going low to the end of
write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the the /CS1 low transition and CS2 high transition occur simultaneously with the /WE low transition
or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Rev 13 / Apr. 2001
6