HY62V8100B Datasheet, PDF (2/12 Pages) Hynix Semiconductor – 128K x8 bit 3.3V Low Power CMOS slow SRAM

HY62V8100B Series
DESCRIPTION
The HY62V8100B is a high speed, low power and
1M bit CMOS SRAM organized as 131,072 words
by 8bit. The HY62V8100B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particulary well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(LL-part)
-. 2.0V(min) data retention
• Standard pin configuration
-. 32 SOP - 525mil
-. 32 TSOP-I - 8X20(Standard and Reversed)
-. 32 sTSOP-I - 8X13.4
(Standard and Reversed)
Product
No.
HY62V8100B
HY62V8100B-E
HY62V8100B-I
Voltage
(V)
3.0~3.6
3.0~3.6
3.0~3.6
Speed
(ns)
70/85/100
70/85/100
70/85/100
Operation
Current/Icc(mA)
5
5
5
Standby Current(uA)
LL
10
15
15
Temperature
(°C)
0~70
-25~85(E)
-40~85(I)
Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
PIN CONNECTION
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O1 13
I/O2 14
I/O3 15
Vss 16
32
Vcc
31
30
29
28
27
A15
CS2
/WE
A13
A8
A11
A9
A8
1
2
3
A13 4
/WE
CS2
5
6
26
25
24
23
22
A9
A11
/OE
A10
/CS1
A15 7
Vcc 8
NC 9
A16 10
A14 11
A12 12
21
I/O8
20
I/O7
19
I/O6
18
I/O5
A7 13
A6 14
A5 15
A4 16
17
I/O4
32
31
30
29
/OE
A10
/CS1
DQ8
A11
A9
A8
A13
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
DQ7 /WE
DQ6 CS2
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
A15
Vcc
NC
A16
A14
A12
A7
AA65
A4
5
6
7
8
9
10
11
12
13
14
15
16
32 /OE
31
30
A10
/CS1
29 DQ8
28 DQ7
27 DQ6
26
25
DQ5
DQ4
24
23
Vss
DQ3
22 DQ2
21 DQ1
20 A0
19
18
AA12
17 A3
SOP
TSOP-I
(Standard)
sTSOP-I
(Standard)
PIN DESCRIPTION
BLOCK DIAGRAM
Pin Name
Pin Function
A0
/CS1
Chip Select 1
CS2
Chip Select 2
/WE
Write Enable
/OE
Output Enable
A0 ~ A16
Address Inputs
I/O1 ~ I/O8
Data Inputs / Outputs
Vcc
Power(3.0V~3.6V)
A16
Vss
Ground
/CS1
CS2
/OE
/WE
ROW
DECODER
MEMORY ARRAY
128K x 8
I/O1
I/O8
Rev 13 / Apr. 2001
2