HY62UF16201A Datasheet, PDF (6/11 Pages) Hynix Semiconductor – 128Kx16bit full CMOS SRAM

TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
ADDR
/CS
/UB ,/ LB
/OE
Data
Out
High-Z
tRC
tAA
tACS
tBA
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
READ CYCLE 2(Note 2,3,4)
ADDR
Data
Out
tRC
tAA
tOH
Previous Data
HY62UF16201A Series
tOH
tCHZ(3)
tBHZ(3)
tOHZ(3)
Data Valid
tOH
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
Data
Out
tACS
tCLZ(3)
Data Valid
tCHZ(3)
Notes:
A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and low /UB and/or /LB.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.08 / Mar. 2002
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