HY62LF16404D Datasheet, PDF (6/10 Pages) Hynix Semiconductor – 256Kx16bit full CMOS SRAM

HY62LF16404D Series
TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
ADDR
/CS
tRC
tAA
tACS
/UB ,/ LB
/OE
Data
Out
High-Z
tBA
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
tOH
tCHZ(3)
tBHZ(3)
tOHZ(3)
Data Valid
READ CYCLE 2 (Note 1,2,4)
tRC
ADDR
Data
Out
tAA
tOH
Previous Data
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
tOH
Data Valid
Data
Out
tACS
tCLZ(3)
Data Valid
tCHZ(3)
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS and /UB and/or /LB .
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.03 / Aug.01
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