HY57V561620 Datasheet, PDF (6/13 Pages) Hynix Semiconductor – 4Banks x 4M x 16Bit Synchronous DRAM

HY57V561620(L)T
DC CHARACTERISTICS II (TA=0°C to 70°C, VDD=3.3V ± 0.3V, VSS=0V)
Parameter
Operating Current
Precharge Standby Current
in power down mode
Precharge Standby Current
in non power down mode
Active Standby Current
in power down mode
Active Standby Current
in non power down mode
Burst Mode Operating
Current
Auto Refresh Current
Self Refresh Current
Symbol
Test Condition
Speed
-HP -H
-8
-P
Unit Note
-S
IDD1
Burst Length=1, One bank active
tRAS ≥ tRAS(min),tRP ≥ tRP(min), IO=0mA
120 120 110 100 100 mA
1
IDD2P
IDD2PS
CKE ≤ VIL(max), tCK = min.
CKE ≤ VIL(max), tCK = ∞
2
mA
2
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
IDD2N
Input signals are changed one time during 2clks.
20
All other pins ≥ VDD-0.2V or ≤ 0.2V
mA
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
10
IDD3P
IDD3PS
CKE ≤ VIL(max), tCK = min
CKE ≤ VIL(max), tCK = ∞
3
mA
3
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
IDD3N
Input signals are changed one time during 2clks.
25
All other pins ≥ VDD-0.2V or ≤ 0.2V
mA
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable
15
IDD4
tCK ≥ tCK(min),
tRAS ≥ tRAS(min), IO=0mA
All banks active
150 150 140 120 120 mA
1
IDD5
tRRC ≥ tRRC(min), All banks active
260 260 260 250 250 mA
2
IDD6
CKE ≤ 0.2V
3
mA
3
1.5
mA
4
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY57V561620T-HP/H/8/P/S
4. HY57V561620LT-HP/H/8/P/S
Revision 1.8 / Apr.01