HY628100A Datasheet, PDF (5/9 Pages) Hynix Semiconductor – 128Kx8bit CMOS SRAM

HY628100A Series
TIMING DIAGRAM
READ CYCLE 1
tRC
ADDR
tAA
OE
tOE
tOH
tOLZ
CS1
CS2
Data
Out
High-Z
tACS
tCLZ
tOHZ
tCHZ
Data Valid
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
ADDR
Data
Out
tRC
tAA
tOH
Previous Data
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS1 = VIL, CS2 = VIH.
3. /OE =VIL.
tOH
Data Valid
Rev.05 /Feb.99
5