HY5S5B2CLFP-6E Datasheet, PDF (5/54 Pages) Hynix Semiconductor – 256M (8Mx32bit) Mobile SDRAM

11
256Mbit (8Mx32bit) Mobile SDR Memory
HY5S5B2CLF(P) Series
FEATURES
● Standard SDRAM Protocol
● Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
● MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
● Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Programmable burst length: 1, 2, 4, 8 or full page
● Programmable Burst Type: sequential or interleaved
● Programmable CAS latency of 3 or 2
● Programmable Drive Strength
● Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
● -25^oC ~ 85^oC Operation Temperature
- Extended Temp.: -25^oC ~ 85^oC
● Package Type: 90ball, 0.8mm pitch FBGA (Lead Free, Lead)
HY5S5B2CLFP: Lead Free
Rev 1.5 / Aug. 2008
5