HY5S5B2CLFP-6E Datasheet, PDF (2/54 Pages) Hynix Semiconductor – 256M (8Mx32bit) Mobile SDRAM

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256Mbit (8Mx32bit) Mobile SDR Memory
HY5S5B2CLF(P) Series
Document Title
4Bank x 2M x 32bits Synchronous DRAM
Revision History
Revision No.
0.1
0.2
1.0
1.1
1.2
1.3
1.4
1.5
History
Initial Draft
Initial Draft
Release
Correct IDD5 value:
85mA max -> 110mA max
Insert (Page11)
DPD specification [IDD7: 10uA min]
- Updated Auto Refresh cycle during Power-up and
Initialization Sequence (8 cycles to 2 cycles)
- Editorial changes in some descriptions
- Corrected the description of BURST TERMINATE
- Corrected the CJE state on every command
- Typo Corrected.
Draft Date
Nov. 2006
Apr. 2007
June. 2007
June. 2007
July. 2007
May 2008
Jun. 2008
Aug. 2008
Remark
Preliminary
Preliminary
Rev 1.5 / Aug. 2008
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